Digital signal processors (DSP) are well known to include program memory, data memory, an address generation unit, a peripheral device interface, internal data buses, a program unit, and a data arithmetic logic unit (ALU). The data ALU generally further comprises an input register, an output register, and a multiply accumulate unit (MAC).
DSPs provide high speed execution of numerically intensive applications such as digital filtering applications. As is known, digital filtering applications typically include a plurality of multiply and accumulate steps to achieve the desired digital filter. The MAC may execute a significant number of the multiply and accumulate steps in order to complete a single filtering function.
The data ALU further includes an accumulator register which receives intermediate resultants from the MAC and provides the intermediate resultants back to the MAC for the additional multiply and accumulation steps. Due to hardware constraints, the accumulator register has a fixed bit size. For example, in a Motorola DSP 56100, the accumulator register is 40 bits wide. Other DSPs, however, may have accumulator registers with widths up to 96 bits of capacity.
In the DSP, the data buses also have a fixed bit size which typically does not match the bit capacity of the accumulator. For example, the bit size of a data bus may be 16 bits, 24 bits, or 32 bits. As mentioned, the bit capacity of the accumulator register is 24 bits up to 96 bits. Therefore, the accumulator register is segregated into various portions, one portion of which is provided as an output to the data buses after the completion of an operation while another portion serves as an overflow portion, the respective portions often referred to as the fractional and integer portions. The segregation of these portions and the relationship of the segregation of the portions to one another allows intermediate calculations to exceed in value the size of a valid final result in the fractional portion. However, this relationship is fixed by the hardware.
Due to the size limitations of the accumulator register, some digital filter application calculation results will exceed the total bit capacity of the accumulator register. Once the bit capacity of the accumulator register has been exceeded, an error condition arises and a default value is entered in memory for the particular series of calculations. An overflow of this nature is generally known as a saturation of an operation or of a result. Further, a final calculation may result in a result that exceeds the data bus width. In this situation, a saturation also occurs and another default value is entered into memory instead of the result.
The sizes of the fractional portion, integer portion, and other portions of the accumulator are determined by the hardware used and thus are not programmable by the user of the DSP. Thus, the programmer must develop instructions that perform within the limits defined by the DSP architecture without unduly limiting the performance of the DSP.
A common technique that prevents the accumulator register from saturating is scaling down the input values to the MAC. By scaling down the inputs to the MAC, the resultant is guaranteed not to exceed the maximum bit capacity of the accumulator register. While scaling down prevents accumulator saturation, the precision of the inputs and the resultant is lost due to shifting of data required to scale the inputs. For digital signal processing applications, when precision is reduced, the signal to noise ratio is also reduced. Thus, in such DSP applications requiring a maximum signal to noise ratio, or margin, the lost precision due to scaling is unacceptable.
Therefore, a need exists for a method and apparatus that allows for a saturation value to be programmed by a DSP programmer.